A. Field of the Invention
The present invention relates to semiconductor apparatuses of a dielectric isolation type that use a silicon-on-insulator (hereinafter referred to as a “SOI”) substrate. Specifically, the invention relates to semiconductor apparatuses such as integrated circuits (hereinafter referred to as “IC's”) for electric power conversion represented by high-voltage integrated circuits (hereinafter referred to as “HVIC's”). More specifically, the invention relates to a lateral double-diffused MOSFET (hereinafter referred to as an “LDMOSFET”) of a high breakdown voltage class between 100 V and 1200 V and such a semiconductor device used in the semiconductor apparatuses.
B. Description of the Related Art
A SOI substrate which facilitates isolating devices from each other perfectly by a trench dielectric isolation (insulation for the side area) and by an insulator layer (insulation for the bottom area) has been attracting much attention recently to meet demands for providing power IC's incorporating a high-voltage device therein with a higher breakdown voltage. Formation of a high-voltage power converter IC on a SOI substrate is advantageous for preventing the malfunction caused at the switching by a parasitic device from occurring, for preventing the interference caused by noise from occurring, and for reducing the parasitic capacitance.
The dielectric isolation technique that employs a trench is applicable to the edge structure and the high-voltage junction termination structure (hereinafter referred to as the “HVJT”) in the devices in the IC. Therefore, it is also expected to reduce the IC chip size itself.
FIG. 9(a) is the top plan view of a conventional dielectric-isolation-type semiconductor apparatus. FIG. 9(b) is the cross sectional view along the broken line X-X in FIG. 9(a). In these drawings, SOI substrate 50 is used. SOI substrate 50 includes supporting base 51, dielectric layer 52 on supporting base 51, and n− semiconductor layer 53 on dielectric layer 52. Dielectric layer 52 isolates supporting base 51 and n− semiconductor layer 53 from each other. Isolation trench 54 including a silicon oxide film loaded therein isolates n− semiconductor layer 53 in the lateral direction such that isolation trench 54 marks off n− semiconductor layer 53.
The n− semiconductor layer 53 marked off works as high-potential floating region (herein after referred to as “HV floating region”) 67 including a driver circuit and an output stage device formed therein. High-voltage NMOSFET (hereinafter referred to as “HV NMOSFET”) 70 is formed as a level-shifting device in a predetermined range in n− semiconductor layer 53.
In FIG. 9(b), HV NMOSFET 70 employs n− semiconductor layer 53 for the n− drift drain layer thereof. HV NMOSFET 70 includes, in the central surface portion on the upper side of n− semiconductor layer 53, heavily doped n+ drain layer 59 and n drain buffer later 58, the resistance of which is higher than the n+ drain layer 59 resistance.
Spaced apart from n drain buffer layer 58, p well diffusion layer 55 is formed such that p well diffusion layer 55 surrounds n drain buffer layer 58. In p well diffusion layer 55, n+ source layer 56 and p+ pickup layer 57 are formed.
Gate electrode 61 is formed above n+ source layer 56, p well diffusion layer 55 and the n− drift drain layer (n− semiconductor layer 53) with a gate insulator film interposed between these layers and gate electrode 61. Source electrode 63 and drain electrode 64 are connected to n+ source layer 56 and n+ drain layer 59, respectively. Source electrode 63 and drain electrode 64 are insulated from each other by field oxide film 62. Drain electrode 64 and source electrode 63 extend above the n− drift drain layer (n− semiconductor layer 53) such that drain electrode 64 and source electrode 63 serve as field plates.
As supporting base 51, source electrode 63 and gate electrode 61 are fixed at the ground (GND) potential and a positive bias voltage applied to drain electrode 64 is raised gradually. A depletion layer extends from the pn-junction between p well diffusion layer 55 and n− semiconductor layer 53. Since supporting base 51 is fixed at the GND potential, a depletion layer extends also from the boundary between dielectric layer 52 and n− semiconductor layer 53. Since the depletion layers extend in the lateral and vertical directions in n− semiconductor layer 53, the surface electric field of the n− drift drain layer (n− semiconductor layer 53) is relaxed. This effect is called generally the “RESURF effect”.
The distance Ld of the n− drift drain layer is set to be sufficiently long. The impurity concentration in the n− drift drain layer is adjusted at an optimum value. The extending lengths of the field plates described above are optimized. Even if a high voltage is applied to drain electrode 64, the surface electric field will be relaxed, the electric field will not localize to the pn-junction and no avalanche breakdown will be caused in the semiconductor layer 53 surface due to the optimum designs described above.
The avalanche breakdown occurs on the boundary between n− semiconductor layer 53 and dielectric layer 52. When the RESURF conditions are met, the breakdown voltage Vbr of HV NMOSFET 70 that constitutes the dielectric-isolation-type semiconductor apparatus is expressed generally by the following formula (1).Vbr=Ecr×((d/2)+Tox×∈si/∈ox)  (1)
Here, Ecr is the critical electric field (unit: V/cm), d the n− semiconductor layer thickness (unit: μm), Tox the dielectric layer thickness (unit: μm), ∈si the relative dielectric permeability of silicon, and ∈ox the relative dielectric permeability of the dielectric material.
When n− semiconductor layer 53 is made of silicon and dielectric layer 52 is made of a silicon oxide film, Ecr is replaced by 3×105 V/cm, d by 20 μm, Tox by 5 μm, ∈si by 11.7, and ∈ox by 3.9, then, Vbr will be 750 V.
If the specific resistance distribution in n− semiconductor layer 53, the thickness distribution of dielectric layer 52 and the substantial breakdown voltage of a power MOSFET and such a switching device driven by the HVIC are considered, it will be required for HV NMOSFET 70 and a high-voltage bootstrap diode to exhibit a breakdown voltage of around 750 V at least, when the product specification is 600 V. HV NMOSFET 70 and the high-voltage bootstrap diode are mounted on the HVIC as a level-shifting device.
It is effective to increase the thickness d of n− semiconductor layer 53 or the thickness Tox of dielectric layer 52 as the above-described formula (1) indicates to provide the dielectric-isolation-type semiconductor apparatus with a higher breakdown voltage.
However, there exist certain limitations on the manufacturing process such as the etching width and thickness of the trench and the oxide film formation in the trench. The limitations limit the thickness of n− semiconductor layer 53. The trench insulates the devices from each other in the lateral direction in n− semiconductor layer 53 and marks off n− semiconductor layer 53. Therefore, 10 to 20 μm is the practical value for the thickness d of n− semiconductor layer 53.
When a bonded SOI substrate is used for SOI substrate 50, the wafer warp in the IC manufacturing process causes a more serious problem, as SOI substrate 50 is thicker. As the SOI substrate 50 thickness is larger, the deposition period, during which dielectric layer 52 is deposited in a high-temperature furnace, becomes longer, increasing the manufacturing costs of SOI substrate 50. In addition to this, the thickening of dielectric layer 52 shortens the extension of the depletion layer extending from the junction plane between dielectric layer 52 and n− semiconductor layer 53. Therefore, the RESURF effects described above are reduced. Since the electric field in the surface of the dielectric-isolation-type semiconductor apparatus becomes higher, the breakdown voltage is lowered. Therefore, it will be difficult to mass-produce semiconductor apparatuses exhibiting a higher breakdown voltage and using SOI substrate 50 having the thickness Tox of 6 μm or thicker, if the breakdown voltage, the manufacturing costs of the substrate and the substrate warping are considered.
As described above, HV NMOSFET 70 is formed on SOI substrate 50 including dielectric layer 52 and n− semiconductor layer 53, and the thickness and impurity concentrations thereof are optimized to meet the requirement of realizing a higher breakdown voltage. When HV NMOSFET 70 (n-channel MOSFET) is integrated into a chip for mounting HV NMOSFET 70 on an HVIC and such an IC for electric power conversion, it is necessary to bridge high-voltage wiring (hereinafter referred to as “HV wiring”) 68 from drain electrode 64 of HV NMOSFET 70 working as a level shifter to HV floating region 67 with an aluminum wiring and such a metal wiring. HV floating region 67 is an island-shaped floating region surrounded by isolation trench 66. The reference potential terminal of HV floating region 67 is connected to the low-potential-side terminal of a high-voltage switching device driven by a high-side driver circuit. HV floating region 67 is provided with the high-side driver circuit that drives the high-voltage switching device.
Japanese Patent Publication No. 3489362 describes the arrangement of a wiring from the central electrode (drain electrode) of a high-voltage NMOSFET (hereinafter referred to as an “HV NMOSFET”) isolated by dielectric isolation. The wiring crosses over outer semiconductor layers (an n+ source layer and a p well layer). However, since the n− semiconductor layer potential is drawn by the drain electrode potential, the electric field localizes in the vicinity of the n+ source layer and p well layer. Therefore, the uniform breakdown voltage design is impaired and an avalanche breakdown is caused at a low voltage in the regions below the wiring, causing a low breakdown voltage.
FIG. 10(a) is the plan view of a conventional one-chip inverter of a dielectric isolation type described in Japanese Unexamined Patent Application Publication No. 2005-64472. FIG. 10(b) is the cross sectional view along the single-dotted chain line G-G′ in FIG. 10(a). As shown in FIG. 10(b), high-voltage wiring 153 is bridged from an HV NMOSFET on a SOI substrate crossing over dielectric isolation trench 154, that is, an HVJT. Since high-voltage wiring 153 crosses over the silicon substrate at the ground (GND) potential, Japanese Unexamined Patent Application Publication No. 2005-64472 points out that the dielectric breakdown of interlayer insulator film 155 and dielectric isolation trench 154 is provable.
The interlayer insulator film 155 may be thickened or the opening width of dielectric isolation trench 154 may be widened to prevent dielectric breakdown from occurring. However, these countermeasures make it more difficult to conduct the step of burying a contact, the step of trench etching, the step of filling the trench with a required material, and a machining step. As a result, a stable manufacturing process will not be obtained.
In FIG. 10(b), source electrode 151, drain electrode 152, p well diffusion layer 160, p diffusion layer (RESURF region) 164, and dielectric isolation trench 154 are shown.
T. Fujihira et al., “Proposal of New Interconnection Technique for Very High-Voltage IC's”, Jpn. J. Appl. Phys., (35) 1996, pp. 5655-5663, T. Terashima et al., “A New Level-Shifting Technique by divided RESURF Structure”, ISPSD (International Symposium on Power Semiconductor Devices & ICs), 1997, pp. 57-60, and S. L. Kim et al., “Realization of Robust 600V High Side Gate Drive IC with a New Isolated Self-Shielding Structure”, Proceeding of the 17th International Symposium on Power Semiconductor Devices & ICs, 2005, pp. 143-146 all report on high-voltage wiring techniques (HV interconnection techniques) for high-voltage devices. These three documents each report a junction isolation method that employs an epitaxial substrate for isolating the circumstance below the HV interconnection or a self-isolation method that uses diffusion layers in a usual silicon substrate for isolating the circumstance below the HV interconnection. In documents, there is no description of a HV interconnection that crosses over a dielectric isolation trench or such a device isolation trench. This indicates that the HV interconnection, which crosses over a dielectric isolation trench and such a device isolation trench, causes a leakage current and such various problems due to the electric field localization in the vicinity of the device isolation trench and the impaired isolation performance, posing high technical difficulties.
For bridging an HV wiring from an HV NMOSFET isolated by dielectric isolation to an adjacent or spaced-apart region isolated by dielectric isolation (e.g. a high-voltage floating region), an HV wiring technique with a wire is employed as described in Japanese Unexamined Patent Application Publication No. 2006-313828. This document describes a method for maintaining the breakdown voltage of the semiconductor apparatus at a high value by arranging, in the lamination direction of dielectric layers, another dielectric layer in adjacent to the dielectric layers.
Japanese Unexamined Patent Application Publication No. 2004-200472 describes the formation of a second buried oxide film by etching the bask surface thereof so that the breakdown voltage of a semiconductor apparatus is not determined depending on the dielectric layer thickness Tox nor on the semiconductor layer thickness d.
Japanese Unexamined Patent Application Publication No. 2007-27358 describes the junction structure of a high-voltage semiconductor device and a high-voltage floating region isolated by dielectric isolation. In the junction structure, multiple isolation trenches and the high-voltage semiconductor device are formed in contact with each other as shown in FIG. 11.
FIG. 12(a) is a cross sectional view of the semiconductor apparatus disclosed in Japanese Unexamined Patent Application Publication No. 2008-244092. FIG. 12(b) is a top plan view of the semiconductor apparatus disclosed in that document.
Japanese Unexamined Patent Application Publication No. 2008-244092 describes the formation of a p− layer (the layer denoted by “p−” in FIG. 12(a)) of a floating potential arranged in a ring-shape below a high-voltage wiring led out from the drain electrode of a high-voltage LDMOSFET formed on an n− semiconductor layer in a SOI substrate. The p− layer is formed to relax the electric field under the drain wiring of the high-voltage MOSFET having a dielectric isolation structure as shown in FIGS. 12(a) and 12 (b). When a high voltage is applied to the drain electrode in this structure, the lightly doped p− layer is depleted to maintain a high breakdown voltage and the potential distributes with a gradient from an n+ drain layer toward an n+ source layer and the trench.
However, the HV wiring by a wire connection is accompanied by, in applying the dielectric-isolation-type semiconductor apparatus on a SOI substrate to a one-chip inverter, bondings inside the chip for connecting the HV NMOSFET, a level shifter, to the IN (input) terminal of a high-side driver circuit in the high-voltage floating region. Therefore, an additional area is necessary for the inside-the-chip bondings. It is also necessary to add a protector element against electrostatic discharge (ESD) for the IN (input) terminal, enlarging the chip size and increasing the manufacturing costs and assembly costs of the chip.
In the structure described in Japanese Unexamined Patent Application Publication No. 2007-27358, multiple isolation trenches are formed as shown in FIG. 11, such that the isolation trenches penetrate into the central region of the drain in the high-voltage semiconductor device, which is a high-voltage MOSFET. The multiple isolation trenches are arranged continuously from the center of the drain region in the high-voltage MOSFET to the edge area thereof. The isolation trenches formed inside the drift region of the high-voltage MOSFET are arranged perpendicular to (at right angles with respect to) the direction from the gate electrode edge to the drain electrode.
Due to the isolation trench arrangement, when a high voltage is applied to the drain electrode, a leakage current will be caused in the vicinity of the point I shown in FIG. 11 from the source to the drain along the trench side wall, since the isolation trenches are arranged in contact with the drain electrode.
The heavily doped drain layer is in contact with the isolation trenches with low resistance and the isolation trenches are in contact with the heavily doped source layer with low resistance. Therefore, a potential gradient is caused between the point at which the isolation trenches are connected to the drain layer and the point at which the isolation trenches are connected to the source layer. As a result, carriers move along the trench side wall due to the defects existing in the trench side wall, causing a leakage current.
In Japanese Unexamined Patent Application Publication No. 2008-244092, the n drain buffer layer surrounding the heavily doped n+ drain layer formed in the drain region is not in contact with the above-described p− diffusion layer at a floating potential. Therefore, the potential drop in the n− semiconductor layer below the HV wiring has a large gradient as described later with reference to FIG. 7(b). As a result, a large potential difference is caused between the n− semiconductor layer and the high-potential floating region adjoining to the oxide film in the trench crossing below the HV wiring (the J point shown in FIG. 12(b)).
Therefore, in order to prevent the dielectric breakdown and isolation performance impairment of the oxide film in the trench from occurring, it is necessary to increase the trench width as shown in FIG. 12(a). If the trench width is increased, it will take a longer time to deposit insulator films in the trenches and it will be necessary to add a step of flattening the deposited insulator films, causing an increase in the number of manufacturing steps.
The structure according to the invention includes, below an HV wiring connecting an n+ drain layer and a high-voltage floating region crossing over a trench isolation region, a p− diffusion layer (RESURF layer) in contact with an n drain buffer layer surrounding the n+ drain layer, and p+ diffusion layer (stopper region) in contact with the p− diffusion layer. The structure according to the invention is not described in any of the above-described documents.
In view of the foregoing, it would be desirable to obviate the problems described above. It would be also desirable to provide a semiconductor apparatus, including an HV NMOSFET formed on a SOI substrate, a drain in the HV NMOSFET, a source in the HV NMOSFET surrounding the drain, and an HV wiring connected to the drain and connecting the HV NMOSFET to the outside, that facilitates preventing the breakdown voltage lowering due to the HV wiring from causing in the HV NMOSFET, the breakdown of an interlayer insulator film due to the HV wiring from causing and the isolation breakdown voltage lowering due to the HV wiring from causing in the device isolation trench. It also would be desirable to provide a semiconductor apparatus with a small area and with low manufacturing costs.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.